#ifndef __SOPH_VO_SYS_REG_H__
#define __SOPH_VO_SYS_REG_H__
#include <asm/io.h>

/*
 * VO SYS Registers
 */

extern u32  vo_sys_f_base;
extern u32  vo_sys_b_base;
extern u32  top_pll_base;

#define REG_VO_MAC_BASE(x) (vo_sys_f_base + 0x1000 + 0x2000*(x))
#define REG_DISP_DSI_BASE(x) (((x == 0) ? vo_sys_f_base : vo_sys_b_base) + 0x2000)
#define REG_DISP_BASE(x) (vo_sys_f_base + 0x4000 + 0x1000*(x))
#define REG_DSI_WRAP_BASE(x) (vo_sys_b_base + 0x1000*(x))
//GOP
#define REG_DISP_GOP_BASE(x) (REG_DISP_BASE(x))
#define REG_GOP_OFFSET(x) (0x800 + 0x200*(x))
//OSD
#define REG_VO_SYS_OENC_BASE(x) (vo_sys_f_base + 0x6000 + 0x1000*(x))

// ============== TOP CLKGEN ============== //
#define REG_FPLL_CTRL2(x) (top_pll_base + 0x88 + 0x100 * (x))
#define REG_FPLL_CTRL5(x) (top_pll_base + 0x94 + 0x100 * (x))
#define REG_MPLL_CTRL1(x) (top_pll_base + 0xc4 + 0x100 * (x))
// ============== VO SYS ============== //
#define REG_VO_SYS_IP_RESET (vo_sys_f_base + 0x00)
#define REG_VO_SYS_APB_RESET (vo_sys_f_base + 0x04)
#define REG_VO_SYS_INTERRUPT (vo_sys_f_base + 0x08)
#define REG_VO_SYS_AXI_SW (vo_sys_f_base + 0x0C)
#define REG_VO_SYS_CLK_LP (vo_sys_f_base + 0x10)
#define REG_VO_SYS_CLK_CTRL0 (vo_sys_f_base + 0x14)
#define REG_VO_SYS_CLK_CTRL1 (vo_sys_f_base + 0x18)
#define REG_VO_SYS_CTRL_AXI_RT (vo_sys_f_base + 0x1C)
#define REG_VO_SYS_CTRL_AXI_OFF (vo_sys_f_base + 0x20)
#define REG_VO_SYS_CTRL_X2P (vo_sys_f_base + 0x24)
#define REG_VO_SYS_CLK_RATIO0 (vo_sys_f_base + 0x28)
#define REG_VO_SYS_CLK_RATIO1 (vo_sys_f_base + 0x2C)
#define REG_VO_SYS_CLK_RATIO2 (vo_sys_f_base + 0x30)
#define REG_VO_SYS_CTRL_STATUS (vo_sys_f_base + 0x34)
#define REG_VO_SYS_URGENT_SEL (vo_sys_f_base + 0x38)
#define REG_VO_SYS_QOS_OW (vo_sys_f_base + 0x3C)
#define REG_VO_SYS_QOS_VALUE0 (vo_sys_f_base + 0x40)
#define REG_VO_SYS_QOS_VALUE1 (vo_sys_f_base + 0x44)
#define REG_VO_SYS_QOS_VALUE2 (vo_sys_f_base + 0x48)
#define REG_VO_SYS_QOS_OFFSET0 (vo_sys_f_base + 0x4C)
#define REG_VO_SYS_QOS_OFFSET1 (vo_sys_f_base + 0x50)
#define REG_VO_SYS_QOS_OFFSET2 (vo_sys_f_base + 0x54)
#define REG_VO_SYS_QOS_URGENT_HI_TH0 (vo_sys_f_base + 0x58)
#define REG_VO_SYS_QOS_URGENT_HI_TH1 (vo_sys_f_base + 0x5C)
#define REG_VO_SYS_QOS_URGENT_HI_TH2 (vo_sys_f_base + 0x60)
#define REG_VO_SYS_QOS_URGENT_HI_TH3 (vo_sys_f_base + 0x64)
#define REG_VO_SYS_AXI_RT_FAB_PRI_MODE (vo_sys_f_base + 0x68)
#define REG_VO_SYS_AXI_RT_FAB_PRI_FIX0 (vo_sys_f_base + 0x6C)
#define REG_VO_SYS_AXI_RT_FAB_PRI_FIX1 (vo_sys_f_base + 0x70)
#define REG_VO_SYS_AXI_RT_FAB_PRI_VALUE0 (vo_sys_f_base + 0x74)
#define REG_VO_SYS_AXI_RT_FAB_PRI_VALUE1 (vo_sys_f_base + 0x78)
#define REG_VO_SYS_AXI_RT_FAB_PRI_VALUE2 (vo_sys_f_base + 0x7C)
#define REG_VO_SYS_QOS_URGENT_LOW_TH0 (vo_sys_f_base + 0x80)
#define REG_VO_SYS_QOS_URGENT_LOW_TH1 (vo_sys_f_base + 0x84)
#define REG_VO_SYS_QOS_URGENT_LOW_TH2 (vo_sys_f_base + 0x88)
#define REG_VO_SYS_RT_AXI_MON_M1 (vo_sys_f_base + 0x90)
#define REG_VO_SYS_RT_AXI_MON_M2 (vo_sys_f_base + 0x94)
#define REG_VO_SYS_RT_AXI_MON_M3 (vo_sys_f_base + 0x98)
#define REG_VO_SYS_RT_AXI_MON_M4 (vo_sys_f_base + 0x9C)
#define REG_VO_SYS_HDMI_PHY_CTRL (vo_sys_f_base + 0xE0)
#define REG_VO_SYS_HDMI_PHY_STATUS (vo_sys_f_base + 0xE4)
#define REG_VO_SYS_HDMI_PHY_BIST_CTL (vo_sys_f_base + 0xE8)
#define REG_VO_SYS_X2P_BUSY_EN (vo_sys_f_base + 0xEC)
#define REG_VO_SYS_VO_DBG0 (vo_sys_f_base + 0x100)
#define REG_VO_SYS_VO_DBG1 (vo_sys_f_base + 0x104)
#define REG_VO_SYS_VO_DBG2 (vo_sys_f_base + 0x108)
#define REG_VO_SYS_VO_DBG3 (vo_sys_f_base + 0x10C)
#define REG_VO_SYS_VO_DUMMY0 (vo_sys_f_base + 0x110)
#define REG_VO_SYS_VO_DUMMY1 (vo_sys_f_base + 0x114)
#define REG_VO_SYS_VO_DUMMY2 (vo_sys_f_base + 0x118)
#define REG_VO_SYS_VO_DUMMY3 (vo_sys_f_base + 0x11C)
#define REG_VO_SYS_AXI_ADDR_EXT_OW (vo_sys_f_base + 0x120)
#define REG_VO_SYS_AXI_ADDR_EXT0 (vo_sys_f_base + 0x124)
#define REG_VO_SYS_AXI_ADDR_EXT1 (vo_sys_f_base + 0x128)
#define REG_VO_SYS_AXI_ADDR_EXT2 (vo_sys_f_base + 0x12C)
#define REG_VO_SYS_AXI_ADDR_EXT3 (vo_sys_f_base + 0x130)
#define REG_VO_SYS_V2DE0_RD_BW_LIMIT (vo_sys_f_base + 0x134)
#define REG_VO_SYS_V2DE0_WR_BW_LIMIT (vo_sys_f_base + 0x138)
#define REG_VO_SYS_V2DE1_RD_BW_LIMIT (vo_sys_f_base + 0x13C)
#define REG_VO_SYS_V2DE1_WR_BW_LIMIT (vo_sys_f_base + 0x140)
#define REG_VO_SYS_RT_AXI_MON_M1_L (vo_sys_f_base + 0x200)
#define REG_VO_SYS_RT_AXI_MON_M1_H (vo_sys_f_base + 0x204)
#define REG_VO_SYS_RT_AXI_MON_M2_L (vo_sys_f_base + 0x208)
#define REG_VO_SYS_RT_AXI_MON_M2_H (vo_sys_f_base + 0x20C)
#define REG_VO_SYS_RT_AXI_MON_M3_L (vo_sys_f_base + 0x210)
#define REG_VO_SYS_RT_AXI_MON_M3_H (vo_sys_f_base + 0x214)
#define REG_VO_SYS_RT_AXI_MON_M4_L (vo_sys_f_base + 0x218)
#define REG_VO_SYS_RT_AXI_MON_M4_H (vo_sys_f_base + 0x21C)
#define REG_VO_SYS_RT_AXI_MON_M5_L (vo_sys_f_base + 0x220)
#define REG_VO_SYS_RT_AXI_MON_M5_H (vo_sys_f_base + 0x224)
#define REG_VO_SYS_RT_AXI_MON_M6_L (vo_sys_f_base + 0x228)
#define REG_VO_SYS_RT_AXI_MON_M6_H (vo_sys_f_base + 0x22C)
#define REG_VO_SYS_RT_AXI_MON_M7_L (vo_sys_f_base + 0x230)
#define REG_VO_SYS_RT_AXI_MON_M7_H (vo_sys_f_base + 0x234)
#define REG_VO_SYS_RT_AXI_MON_M8_L (vo_sys_f_base + 0x238)
#define REG_VO_SYS_RT_AXI_MON_M8_H (vo_sys_f_base + 0x23C)
#define REG_VO_SYS_RT_AXI_MON_M9_L (vo_sys_f_base + 0x240)
#define REG_VO_SYS_RT_AXI_MON_M9_H (vo_sys_f_base + 0x244)
#define REG_VO_SYS_RT_AXI_MON_M10_L (vo_sys_f_base + 0x248)
#define REG_VO_SYS_RT_AXI_MON_M10_H (vo_sys_f_base + 0x24C)
#define REG_VO_SYS_RT_AXI_MON_M11_L (vo_sys_f_base + 0x250)
#define REG_VO_SYS_RT_AXI_MON_M11_H (vo_sys_f_base + 0x254)
#define REG_VO_SYS_RT_AXI_MON_M12_L (vo_sys_f_base + 0x258)
#define REG_VO_SYS_RT_AXI_MON_M12_H (vo_sys_f_base + 0x25C)
#define REG_VO_SYS_OFF_AXI_MON_M1_L (vo_sys_f_base + 0x260)
#define REG_VO_SYS_OFF_AXI_MON_M1_H (vo_sys_f_base + 0x264)
#define REG_VO_SYS_OFF_AXI_MON_M2_L (vo_sys_f_base + 0x268)
#define REG_VO_SYS_OFF_AXI_MON_M2_H (vo_sys_f_base + 0x26C)
#define REG_VO_SYS_OFF_AXI_MON_M3_L (vo_sys_f_base + 0x270)
#define REG_VO_SYS_OFF_AXI_MON_M3_H (vo_sys_f_base + 0x274)
#define REG_VO_SYS_OFF_AXI_MON_M4_L (vo_sys_f_base + 0x278)
#define REG_VO_SYS_OFF_AXI_MON_M4_H (vo_sys_f_base + 0x27C)
#define REG_VO_SYS_OFF_AXI_MON_M5_L (vo_sys_f_base + 0x280)
#define REG_VO_SYS_OFF_AXI_MON_M5_H (vo_sys_f_base + 0x284)
#define REG_VO_SYS_OFF_AXI_MON_M6_L (vo_sys_f_base + 0x288)
#define REG_VO_SYS_OFF_AXI_MON_M6_H (vo_sys_f_base + 0x28C)
#define REG_VO_SYS_CLK_TEST (vo_sys_f_base + 0x290)
#define REG_VO_SYS_CLK_STATUS (vo_sys_f_base + 0x294)

// ============== VO MAC ============== //
// bt interface
#define REG_VO_MAC_BT_CFG(x) (REG_VO_MAC_BASE(x) + 0x10)
#define REG_VO_MAC_BT_ENC(x) (REG_VO_MAC_BASE(x) + 0x14)
#define REG_VO_MAC_BT_SYNC_CODE(x) (REG_VO_MAC_BASE(x) + 0x18)
#define REG_VO_MAC_BT_BLK_DATA(x) (REG_VO_MAC_BASE(x) + 0x1C)
// i80 interface
#define REG_DISP_MCU_IF_CTRL(x) (REG_VO_MAC_BASE(x) + 0x20)
#define REG_DISP_MCU_SW_CTRL(x) (REG_VO_MAC_BASE(x) + 0x24)
#define REG_DISP_MCU_STATUS(x) (REG_VO_MAC_BASE(x) + 0x28)
#define REG_DISP_HW_MCU_AUTO(x) (REG_VO_MAC_BASE(x) + 0x30)
#define REG_DISP_HW_MCU_CMD(x) (REG_VO_MAC_BASE(x) + 0x34)
#define REG_DISP_HW_MCU_CMD0(x) (REG_VO_MAC_BASE(x) + 0x38)
#define REG_DISP_HW_MCU_CMD1(x) (REG_VO_MAC_BASE(x) + 0x3C)
#define REG_DISP_HW_MCU_CMD2(x) (REG_VO_MAC_BASE(x) + 0x40)
#define REG_DISP_HW_MCU_CMD3(x) (REG_VO_MAC_BASE(x) + 0x44)
#define REG_DISP_HW_MCU_CMD4(x) (REG_VO_MAC_BASE(x) + 0x48)
#define REG_DISP_HW_MCU_CMD5(x) (REG_VO_MAC_BASE(x) + 0x4C)
#define REG_DISP_HW_MCU_CMD6(x) (REG_VO_MAC_BASE(x) + 0x50)
#define REG_DISP_HW_MCU_CMD7(x) (REG_VO_MAC_BASE(x) + 0x54)
#define REG_DISP_HW_MCU_SW_OV(x) (REG_VO_MAC_BASE(x) + 0x58)
// lvds interface
#define REG_VO_MAC_LVDSTX(x) (REG_VO_MAC_BASE(x) + 0x5C)
//Serial RGB interface
#define REG_DISP_SRGB_CTRL(x) (REG_VO_MAC_BASE(x) + 0x60)
//vo mux
#define REG_VO_MAC_VO_MUX(x) (REG_VO_MAC_BASE(x) + 0x70)
#define REG_VO_MAC_VO_MUX0(x) (REG_VO_MAC_BASE(x) + 0x90)
#define REG_VO_MAC_VO_MUX1(x) (REG_VO_MAC_BASE(x) + 0x94)
#define REG_VO_MAC_VO_MUX2(x) (REG_VO_MAC_BASE(x) + 0x98)
#define REG_VO_MAC_VO_MUX3(x) (REG_VO_MAC_BASE(x) + 0x9C)
#define REG_VO_MAC_VO_MUX4(x) (REG_VO_MAC_BASE(x) + 0xA0)
#define REG_VO_MAC_VO_MUX5(x) (REG_VO_MAC_BASE(x) + 0xA4)
#define REG_VO_MAC_VO_MUX6(x) (REG_VO_MAC_BASE(x) + 0xA8)
#define REG_VO_MAC_VO_MUX7(x) (REG_VO_MAC_BASE(x) + 0xAC)
#define REG_VO_MAC_VO_MUX8(x) (REG_VO_MAC_BASE(x) + 0xB0)
#define REG_VO_MAC_VO_MUX9(x) (REG_VO_MAC_BASE(x) + 0xB4)
#define REG_VO_MAC_VO_MUXA(x) (REG_VO_MAC_BASE(x) + 0xB8)

// ============== DISP ============== //
#define REG_DISP_CFG(x) (REG_DISP_BASE(x) + 0x00)
#define REG_DISP_TOTAL(x) (REG_DISP_BASE(x) + 0x04)
#define REG_DISP_VSYNC(x) (REG_DISP_BASE(x) + 0x08)
#define REG_DISP_VFDE(x) (REG_DISP_BASE(x) + 0x0C)
#define REG_DISP_VMDE(x) (REG_DISP_BASE(x) + 0x10)
#define REG_DISP_HSYNC(x) (REG_DISP_BASE(x) + 0x14)
#define REG_DISP_HFDE(x) (REG_DISP_BASE(x) + 0x18)
#define REG_DISP_HMDE(x) (REG_DISP_BASE(x) + 0x1C)
#define REG_DISP_RD_TH(x) (REG_DISP_BASE(x) + 0x2C)
#define REG_DISP_FIFO(x) (REG_DISP_BASE(x) + 0x30)
#define REG_DISP_ADDR0_L(x) (REG_DISP_BASE(x) + 0x34)
#define REG_DISP_ADDR0_H(x) (REG_DISP_BASE(x) + 0x38)
#define REG_DISP_ADDR1_L(x) (REG_DISP_BASE(x) + 0x3C)
#define REG_DISP_ADDR1_H(x) (REG_DISP_BASE(x) + 0x40)
#define REG_DISP_ADDR2_L(x) (REG_DISP_BASE(x) + 0x44)
#define REG_DISP_ADDR2_H(x) (REG_DISP_BASE(x) + 0x48)
#define REG_DISP_PITCH_Y(x) (REG_DISP_BASE(x) + 0x4C)
#define REG_DISP_PITCH_C(x) (REG_DISP_BASE(x) + 0x50)
#define REG_DISP_OFFSET(x) (REG_DISP_BASE(x) + 0x54)
#define REG_DISP_SIZE(x) (REG_DISP_BASE(x) + 0x58)
#define REG_DISP_OUT_CSC0(x) (REG_DISP_BASE(x) + 0x5C)
#define REG_DISP_OUT_CSC1(x) (REG_DISP_BASE(x) + 0x60)
#define REG_DISP_OUT_CSC2(x) (REG_DISP_BASE(x) + 0x64)
#define REG_DISP_OUT_CSC3(x) (REG_DISP_BASE(x) + 0x68)
#define REG_DISP_OUT_CSC4(x) (REG_DISP_BASE(x) + 0x6C)
#define REG_DISP_OUT_CSC_SUB(x) (REG_DISP_BASE(x) + 0x70)
#define REG_DISP_OUT_CSC_ADD(x) (REG_DISP_BASE(x) + 0x74)
#define REG_DISP_IN_CSC0(x) (REG_DISP_BASE(x) + 0x78)
#define REG_DISP_IN_CSC1(x) (REG_DISP_BASE(x) + 0x7C)
#define REG_DISP_IN_CSC2(x) (REG_DISP_BASE(x) + 0x80)
#define REG_DISP_IN_CSC3(x) (REG_DISP_BASE(x) + 0x84)
#define REG_DISP_IN_CSC4(x) (REG_DISP_BASE(x) + 0x88)
#define REG_DISP_IN_CSC_SUB(x) (REG_DISP_BASE(x) + 0x8C)
#define REG_DISP_IN_CSC_ADD(x) (REG_DISP_BASE(x) + 0x90)

#define REG_DISP_PAT_CFG(x) (REG_DISP_BASE(x) + 0x94)
#define REG_DISP_PAT_COLOR0(x) (REG_DISP_BASE(x) + 0x98)
#define REG_DISP_PAT_COLOR1(x) (REG_DISP_BASE(x) + 0x9C)
#define REG_DISP_PAT_COLOR2(x) (REG_DISP_BASE(x) + 0xA0)
#define REG_DISP_PAT_COLOR3(x) (REG_DISP_BASE(x) + 0xA4)
#define REG_DISP_PAT_COLOR4(x) (REG_DISP_BASE(x) + 0xA8)

#define REG_DISP_DBG(x) (REG_DISP_BASE(x) + 0xAC)
#define REG_DISP_AXI_ST(x) (REG_DISP_BASE(x) + 0xB0)
#define REG_DISP_CATCH(x) (REG_DISP_BASE(x) + 0xC0)
#define REG_DISP_CHECKSUM0(x) (REG_DISP_BASE(x) + 0xC4)
#define REG_DISP_CHECKSUM1(x) (REG_DISP_BASE(x) + 0xC8)
#define REG_DISP_CHECKSUM2(x) (REG_DISP_BASE(x) + 0xCC)
#define REG_DISP_DUMMY(x) (REG_DISP_BASE(x) + 0xF8)
#define REG_DISP_DUMMY(x) (REG_DISP_BASE(x) + 0xF8)
#define REG_DISP_DUMMY(x) (REG_DISP_BASE(x) + 0xF8)

// GAMMA
#define REG_DISP_GAMMA_CTRL(x) (REG_DISP_BASE(x) + 0x180)
#define REG_DISP_GAMMA_WR_LUT(x) (REG_DISP_BASE(x) + 0x184)
#define REG_DISP_GAMMA_RD_LUT(x) (REG_DISP_BASE(x) + 0x188)

// COVER
#define REG_DISP_COVER_CFG(x, y) (REG_DISP_GOP_BASE(x) + 0x0C*y + 0x280)
#define REG_DISP_COVER_SIZE(x, y) (REG_DISP_GOP_BASE(x) + 0x0C*y + 0x284)
#define REG_DISP_COVER_COLOR(x, y) (REG_DISP_GOP_BASE(x) + 0x0C*y + 0x288)

// ODMA
#define REG_DISP_ODMA_CFG(x) (REG_DISP_BASE(x) + 0x318)
#define REG_DISP_ODMA_Y_L(x) (REG_DISP_BASE(x) + 0x31C)
#define REG_DISP_ODMA_Y_H(x) (REG_DISP_BASE(x) + 0x320)
#define REG_DISP_ODMA_U_L(x) (REG_DISP_BASE(x) + 0x324)
#define REG_DISP_ODMA_U_H(x) (REG_DISP_BASE(x) + 0x328)
#define REG_DISP_ODMA_V_L(x) (REG_DISP_BASE(x) + 0x32C)
#define REG_DISP_ODMA_V_H(x) (REG_DISP_BASE(x) + 0x330)
#define REG_DISP_ODMA_PITCH_Y(x) (REG_DISP_BASE(x) + 0x334)
#define REG_DISP_ODMA_PITCH_C(x) (REG_DISP_BASE(x) + 0x338)

#define REG_DISP_ODMA_X_STR(x) (REG_DISP_BASE(x) + 0x33C)
#define REG_DISP_ODMA_Y_STR(x) (REG_DISP_BASE(x) + 0x340)
#define REG_DISP_ODMA_WIDETH(x) (REG_DISP_BASE(x) + 0x344)
#define REG_DISP_ODMA_HEIGHT(x) (REG_DISP_BASE(x) + 0x348)

#define REG_DISP_ODMA_DEBUG(x) (REG_DISP_BASE(x) + 0x350)
#define REG_DISP_ODMA_LINE_TARGET(x) (REG_DISP_BASE(x) + 0x354)
#define REG_DISP_ODMA_CYCLE_LINE(x) (REG_DISP_BASE(x) + 0x358)

#define REG_DISP_ODMA_LATCH_LINE(x) (REG_DISP_BASE(x) + 0x35C)
#define REG_DISP_ODMA_FIFO_CFG(x) (REG_DISP_BASE(x) + 0x360)
#define REG_DISP_ODMA_FIFO_WH(x) (REG_DISP_BASE(x) + 0x364)
#define REG_DISP_ODMA_FIFO_LMT(x) (REG_DISP_BASE(x) + 0x368)

// INTRU
#define REG_DISP_DEBUG_STATUS(x) (REG_DISP_BASE(x) + 0x370)
#define REG_DISP_INTER_SEL(x) (REG_DISP_BASE(x) + 0x374)
#define REG_DISP_INTER_CLR(x) (REG_DISP_BASE(x) + 0x378)

// ODMA CSC
#define REG_CSC_ODMA_1(x) (REG_DISP_BASE(x) + 0x380)
#define REG_CSC_ODMA_2(x) (REG_DISP_BASE(x) + 0x384)
#define REG_CSC_ODMA_3(x) (REG_DISP_BASE(x) + 0x388)
#define REG_CSC_ODMA_4(x) (REG_DISP_BASE(x) + 0x38C)
#define REG_CSC_ODMA_5(x) (REG_DISP_BASE(x) + 0x390)
#define REG_CSC_ODMA_6(x) (REG_DISP_BASE(x) + 0x394)
#define REG_CSC_ODMA_7(x) (REG_DISP_BASE(x) + 0x398)
#define REG_CSC_ODMA_8(x) (REG_DISP_BASE(x) + 0x39C)

//SWAP RGB
#define REG_DISP_SWAP_RGB(x) (REG_DISP_BASE(x) + 0x3A0)

//LINE BUFFER
#define REG_DISP_LINE_BUFFER(x) (REG_DISP_BASE(x) + 0x3A4)

// ============== DSI ============== //
#define REG_DSI_MAC_EN(x)  (REG_DISP_DSI_BASE(x) + 0x00)
#define REG_DSI_HS_0(x)    (REG_DISP_DSI_BASE(x) + 0x04)
#define REG_DSI_HS_1(x)    (REG_DISP_DSI_BASE(x) + 0x08)
#define REG_DSI_ESC(x)     (REG_DISP_DSI_BASE(x) + 0x0C)
#define REG_DSI_ESC_TX0(x) (REG_DISP_DSI_BASE(x) + 0x10)
#define REG_DSI_ESC_TX1(x) (REG_DISP_DSI_BASE(x) + 0x14)
#define REG_DSI_ESC_TX2(x) (REG_DISP_DSI_BASE(x) + 0x18)
#define REG_DSI_ESC_TX3(x) (REG_DISP_DSI_BASE(x) + 0x1C)
#define REG_DSI_ESC_RX0(x) (REG_DISP_DSI_BASE(x) + 0x20)
#define REG_DSI_ESC_RX1(x) (REG_DISP_DSI_BASE(x) + 0x24)

// ============== DSI PHY ============== //
#define REG_DSI_PHY_EN(x)             (REG_DSI_WRAP_BASE(x) + 0x00)
#define REG_DSI_PHY_CLK_CFG1(x)       (REG_DSI_WRAP_BASE(x) + 0x04)
#define REG_DSI_PHY_CLK_CFG2(x)       (REG_DSI_WRAP_BASE(x) + 0x08)
#define REG_DSI_PHY_ESC_INIT(x)       (REG_DSI_WRAP_BASE(x) + 0x0C)
#define REG_DSI_PHY_ESC_WAKE(x)       (REG_DSI_WRAP_BASE(x) + 0x10)
#define REG_DSI_PHY_HS_CFG1(x)        (REG_DSI_WRAP_BASE(x) + 0x14)
#define REG_DSI_PHY_HS_CFG2(x)        (REG_DSI_WRAP_BASE(x) + 0x18)
#define REG_DSI_PHY_CAL_CFG(x)        (REG_DSI_WRAP_BASE(x) + 0x1C)
#define REG_DSI_PHY_CAL_NUM(x)        (REG_DSI_WRAP_BASE(x) + 0x20)
#define REG_DSI_PHY_CLK_STATE(x)      (REG_DSI_WRAP_BASE(x) + 0x24)
#define REG_DSI_PHY_DATA0_STATE(x)    (REG_DSI_WRAP_BASE(x) + 0x28)
#define REG_DSI_PHY_DATA12_STATE(x)   (REG_DSI_WRAP_BASE(x) + 0x2C)
#define REG_DSI_PHY_DATA3_STATE(x)    (REG_DSI_WRAP_BASE(x) + 0x30)
#define REG_DSI_PHY_LPCD_STATE(x)     (REG_DSI_WRAP_BASE(x) + 0x34)
#define REG_DSI_PHY_HS_OV(x)          (REG_DSI_WRAP_BASE(x) + 0x38)
#define REG_DSI_PHY_HS_SW1(x)         (REG_DSI_WRAP_BASE(x) + 0x3C)
#define REG_DSI_PHY_HS_SW2(x)         (REG_DSI_WRAP_BASE(x) + 0x40)
#define REG_DSI_PHY_DATA_OV(x)        (REG_DSI_WRAP_BASE(x) + 0x44)
#define REG_DSI_PHY_LPTX_OV(x)        (REG_DSI_WRAP_BASE(x) + 0x4C)
#define REG_DSI_PHY_LPRX_OV(x)        (REG_DSI_WRAP_BASE(x) + 0x4C)
#define REG_DSI_PHY_PD(x)             (REG_DSI_WRAP_BASE(x) + 0x64)
#define REG_DSI_PHY_TXPLL(x)          (REG_DSI_WRAP_BASE(x) + 0x6C)
#define REG_DSI_PHY_REG_8C(x)         (REG_DSI_WRAP_BASE(x) + 0x8C)
#define REG_DSI_PHY_REG_SET(x)        (REG_DSI_WRAP_BASE(x) + 0x90)
#define REG_DSI_PHY_LANE_SEL(x)       (REG_DSI_WRAP_BASE(x) + 0x9C)
#define REG_DSI_PHY_LANE_PN_SWAP(x)   (REG_DSI_WRAP_BASE(x) + 0xA0)
#define REG_DSI_PHY_LVDS_EN(x)        (REG_DSI_WRAP_BASE(x) + 0xB4)
#define REG_DSI_PHY_EXT_GPIO(x)       (REG_DSI_WRAP_BASE(x) + 0xC0)
#define REG_DSI_PHY_GPO_CFG(x)        (REG_DSI_WRAP_BASE(x) + 0xC4)
#define REG_DSI_PHY_GPI_CFG(x)        (REG_DSI_WRAP_BASE(x) + 0xC8)
#define REG_DSI_PHY_GPO_GPI_P(x)      (REG_DSI_WRAP_BASE(x) + 0xD0)
#define REG_DSI_PHY_GPO_GPI_N(x)      (REG_DSI_WRAP_BASE(x) + 0xD4)

#define REG_DSI_PHY_DUMMY_0(x)        (REG_DSI_WRAP_BASE(x) + 0xF0)
#define REG_DSI_PHY_DUMMY_1(x)        (REG_DSI_WRAP_BASE(x) + 0xF4)
#define REG_DSI_PHY_DUMMY_R0(x)       (REG_DSI_WRAP_BASE(x) + 0xF8)
#define REG_DSI_PHY_DUMMY_R1(x)       (REG_DSI_WRAP_BASE(x) + 0xFC)
#define REG_DSI_PHY_TXPLL_SETUP(x)    (REG_DSI_WRAP_BASE(x) + 0x100)
#define REG_DSI_PHY_TEST_CLK_EXT(x)   (REG_DSI_WRAP_BASE(x) + 0x104)
#define REG_DSI_PHY_EN_MIPI_CFG(x)    (REG_DSI_WRAP_BASE(x) + 0x108)
#define REG_DSI_PHY_EN_LVDS_CFG(x)    (REG_DSI_WRAP_BASE(x) + 0x10C)
#define REG_DSI_PHY_EN_CLK_BUS(x)     (REG_DSI_WRAP_BASE(x) + 0x110)
#define REG_DSI_PHY_CSEL_PREAMP(x)    (REG_DSI_WRAP_BASE(x) + 0x114)
#define REG_DSI_PHY_RSEL_PREAMP(x)    (REG_DSI_WRAP_BASE(x) + 0x118)
#define REG_DSI_PHY_EN_PREAMP_HSPEED(x)  (REG_DSI_WRAP_BASE(x) + 0x11C)
#define REG_DSI_PHY_EN_CLKRX_SOURCE(x)   (REG_DSI_WRAP_BASE(x) + 0x120)
#define REG_DSI_PHY_EN_RTERM(x)          (REG_DSI_WRAP_BASE(x) + 0x124)
#define REG_DSI_PHY_EN_VCM_DET(x)        (REG_DSI_WRAP_BASE(x) + 0x128)
#define REG_DSI_PHY_SEL_RXCLK_SKEW(x)    (REG_DSI_WRAP_BASE(x) + 0x12C)
#define REG_DSI_PHY_SEL_RXDATA_SKEW(x)   (REG_DSI_WRAP_BASE(x) + 0x130)
#define REG_DSI_PHY_SEL_RXDATA_SKEW4(x)  (REG_DSI_WRAP_BASE(x) + 0x134)
#define REG_DSI_PHY_EN_MIPI_DE_DRV(x)    (REG_DSI_WRAP_BASE(x) + 0x138)
#define REG_DSI_PHY_EN_MIPI_TRIM(x)      (REG_DSI_WRAP_BASE(x) + 0x13C)
#define REG_DSI_PHY_D0_PRBS9_CFG(x)      (REG_DSI_WRAP_BASE(x) + 0x140)
#define REG_DSI_PHY_D0_PRBS9_DEBUG(x)    (REG_DSI_WRAP_BASE(x) + 0x144)
#define REG_DSI_PHY_D1_PRBS9_CFG(x)      (REG_DSI_WRAP_BASE(x) + 0x148)
#define REG_DSI_PHY_D1_PRBS9_DEBUG(x)    (REG_DSI_WRAP_BASE(x) + 0x14C)
#define REG_DSI_PHY_D2_PRBS9_CFG(x)      (REG_DSI_WRAP_BASE(x) + 0x150)
#define REG_DSI_PHY_D2_PRBS9_DEBUG(x)    (REG_DSI_WRAP_BASE(x) + 0x154)
#define REG_DSI_PHY_D3_PRBS9_CFG(x)      (REG_DSI_WRAP_BASE(x) + 0x158)
#define REG_DSI_PHY_D3_PRBS9_DEBUG(x)    (REG_DSI_WRAP_BASE(x) + 0x15C)
#define REG_DSI_PHY_POWER_DOWN_CFG(x)    (REG_DSI_WRAP_BASE(x) + 0x160)
#define REG_DSI_PHY_EN_MIPI_DRV(x)       (REG_DSI_WRAP_BASE(x) + 0x164)
#define REG_DSI_PHY_EN_TX_RTERM(x)       (REG_DSI_WRAP_BASE(x) + 0x168)


// OSD encoder
#define REG_VO_SYS_OENC_RST(x) (REG_VO_SYS_OENC_BASE(x) + 0x00)
#define REG_VO_SYS_OENC_INT_GO(x) (REG_VO_SYS_OENC_BASE(x) + 0x04)
#define REG_VO_SYS_OENC_HEADER_CFG(x) (REG_VO_SYS_OENC_BASE(x) + 0x08)
#define REG_VO_SYS_OENC_CFG(x) (REG_VO_SYS_OENC_BASE(x) + 0x10)
#define REG_VO_SYS_OENC_RANGE(x) (REG_VO_SYS_OENC_BASE(x) + 0x14)
#define REG_VO_SYS_OENC_PITCH(x) (REG_VO_SYS_OENC_BASE(x) + 0x18)
#define REG_VO_SYS_OENC_SRC_ADDR(x) (REG_VO_SYS_OENC_BASE(x) + 0x20)
#define REG_VO_SYS_OENC_WPROT_LADDR(x) (REG_VO_SYS_OENC_BASE(x) + 0x30)
#define REG_VO_SYS_OENC_WPROT_UADDR(x) (REG_VO_SYS_OENC_BASE(x) + 0x38)
#define REG_VO_SYS_OENC_BSO_ADDR(x) (REG_VO_SYS_OENC_BASE(x) + 0x40)
#define REG_VO_SYS_OENC_LIMIT_BSZ(x) (REG_VO_SYS_OENC_BASE(x) + 0x48)
#define REG_VO_SYS_OENC_BSO_SZ(x) (REG_VO_SYS_OENC_BASE(x) + 0x4C)
#define REG_VO_SYS_OENC_WPROT_DEBUG(x) (REG_VO_SYS_OENC_BASE(x) + 0x50)

// DISP GOP
//The z below represents different ow
#define REG_DISP_GOP_FMT(x, y, z) (REG_DISP_GOP_BASE(x) + REG_GOP_OFFSET(y) + 0x20*z + 0x00)
#define REG_DISP_GOP_H_RANGE(x, y, z) (REG_DISP_GOP_BASE(x) + REG_GOP_OFFSET(y) + 0x20*z + 0x04)
#define REG_DISP_GOP_V_RANGE(x, y, z) (REG_DISP_GOP_BASE(x) + REG_GOP_OFFSET(y) + 0x20*z + 0x08)
#define REG_DISP_GOP_ADDR_L(x, y, z) (REG_DISP_GOP_BASE(x) + REG_GOP_OFFSET(y) + 0x20*z + 0x0c)
#define REG_DISP_GOP_ADDR_H(x, y, z) (REG_DISP_GOP_BASE(x) + REG_GOP_OFFSET(y) + 0x20*z + 0x10)
#define REG_DISP_GOP_CROP_PITCH(x, y, z) (REG_DISP_GOP_BASE(x) + REG_GOP_OFFSET(y) + 0x20*z + 0x14)
#define REG_DISP_GOP_SIZE(x, y, z) (REG_DISP_GOP_BASE(x) + REG_GOP_OFFSET(y) + 0x20*z + 0x18)
#define REG_DISP_GOP_CFG(x, y) (REG_DISP_GOP_BASE(x) + REG_GOP_OFFSET(y) + 0x100)
#define REG_DISP_GOP_256LUT0(x, y) (REG_DISP_GOP_BASE(x) + REG_GOP_OFFSET(y) + 0x104)
#define REG_DISP_GOP_256LUT1(x, y) (REG_DISP_GOP_BASE(x) + REG_GOP_OFFSET(y) + 0x108)
#define REG_DISP_GOP_COLORKEY(x, y) (REG_DISP_GOP_BASE(x) + REG_GOP_OFFSET(y) + 0x10c)
#define REG_DISP_GOP_FONTCOLOR(x, y) (REG_DISP_GOP_BASE(x) + REG_GOP_OFFSET(y) + 0x110)
#define REG_DISP_GOP_FONTBOX_CTRL(x, y) (REG_DISP_GOP_BASE(x) + REG_GOP_OFFSET(y) + 0x120)
//The z below represents different fontbox instance
#define REG_DISP_GOP_FONTBOX_CFG(x, y, z) (REG_DISP_GOP_BASE(x) + REG_GOP_OFFSET(y) + 0x10*z + 0x124)
#define REG_DISP_GOP_FONTBOX_INIT(x, y, z) (REG_DISP_GOP_BASE(x) + REG_GOP_OFFSET(y) + 0x10*z + 0x128)
#define REG_DISP_GOP_FONTBOX_REC(x, y, z) (REG_DISP_GOP_BASE(x) + REG_GOP_OFFSET(y) + 0x10*z + 0x12c)
#define REG_DISP_GOP_BW_LIMIT(x, y) (REG_DISP_GOP_BASE(x) + REG_GOP_OFFSET(y) + 0x140)
#define REG_DISP_GOP_DEC_CTRL(x, y) (REG_DISP_GOP_BASE(x) + REG_GOP_OFFSET(y) + 0x150)
#define REG_DISP_GOP_DEC_DEBUG(x, y) (REG_DISP_GOP_BASE(x) + REG_GOP_OFFSET(y) + 0x154)
//The z below represents length
#define REG_DISP_GOP_16LUT(x, y, z) (REG_DISP_GOP_BASE(x) + REG_GOP_OFFSET(y) + 0x4*z + 0x160)

enum drm_intf {
    DRM_INTF_DISP0,
    DRM_INTF_DISP1,
    DRM_INTF_HDMI,
    DRM_INTF_BUTT,
};

u32 _reg_read(uintptr_t addr);
void _reg_write(uintptr_t addr, u32 value);
void _reg_write_mask(uintptr_t addr, u32 mask, u32 data);
void extend_axi_to_36bit(u32 high_bit, enum drm_intf intf);

#endif /* __SOPH_VO_SYS_REG_H__ */
